Published April 8, 2002
by Springer .
Written in English
Lecture Notes in Computer Science
|The Physical Object|
|Number of Pages||126|
ISBN: X OCLC Number: Description: xii, pages: illustrations ; 24 cm: Contents: 1. Introduction Fault Models and Fault-Behavior of Processor Structures On-line Check Technology for Processor Components On-line Check Technology for Processor Control Signals Fast Processor Recover Techniques with Micro Rollback COVID Resources. Reliable information about the coronavirus (COVID) is available from the World Health Organization (current situation, international travel).Numerous and frequently-updated resource results are available from this ’s WebJunction has pulled together information and resources to assist library staff as they consider how to handle coronavirus. Buy On-line Error Detection and Fast Recover Techniques for Dependable Embedded Processors (Lecture Notes in Computer Science) by Pflanz, Matthias (ISBN. Our technique combines the ideas of existing techniques in order to increase the fault detection ratio, decrease the imposed code size and execution time overhead. As the name gives away, we opt to duplicate the entire code base and place comparison instructions in critical basic blocks only.
2 Klicks für mehr Datenschutz: Erst wenn Sie hier klicken, wird der Button aktiv und Sie können Ihre Empfehlung an Facebook senden. Schon beim Aktivieren werden Daten an Dritte übertragen – siehe i. An obvious problem is the case of faulty control signals for fault-free components. Encoding and/or prediction techniques for component checks are useless if the wrong function is observed. In order to count these events, ConFirm leverages the Hardware Performance Counters (HPCs), which readily exist in many embedded processors. We evaluate the detection capability and performance overhead of the proposed technique on various types of firmware running on ARM- and PowerPC-based embedded processors. Pflanz M and Vierhaus H () Online Check and Recovery Techniques for Dependable Embedded Processors, IEEE Micro, , (), Online publication date: 1-Sep Youn H, Oh C, Choo H, Chung J and Lee D () An Efficient Algorithm-Based Fault Tolerance Design Using the Weighted Data-Check Relationship, IEEE Transactions on Computers,
This paper proposes the Cross-Parity check as a method for an on-line detection of multiple bit-errors in registers or register files of microprocessors. Transient or ‘soft’ errors caused by radiation as single event upsets (SEUs) or electromagnetic coupling are in the focus of this work. The precursory proposed techniques for on-line observation of processor components and signals was developed in order to detect errors within a single clock cycle. According to Fig. 16, this is a. • Fault recovery technique's success depends on the detection of faults accurately and as early as possible. • Three classes of recovery procedures: • Full Recovery It requires all the aspects of fault tolerant computing. • Degraded recovery: Also referred as graceful degradation. Similar to full recovery but no subsystem is switched-in. A Computer Science portal for geeks. It contains well written, well thought and well explained computer science and programming articles, quizzes and practice/competitive programming/company interview Questions.